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Scalable Coherent Interface
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#	Item
1	Preliminary Simulations of a SCI based Clustered Database Machine Haakon Bryhni and Stein Gjessing Department of Informatics, University of Oslo, 0316 Oslo, Norway Antonio Schinco, Olivetti Servers R&D, 10010 Scarmagno, Add to Reading List Source URL: www.nik.no Language: English - Date: 2002-05-08 04:37:04 Supercomputers Cache CPU cache Scalable Coherent Interface Latency Throughput Computing Computer memory Computer hardware
2	HIERARCHICAL DIRECTORY CONTROLLERS IN THE NUMACHINE MULTIPROCESSOR by Alexander Grbic Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:44 Cache coherency CPU cache Cache Dynamic random-access memory Memory hierarchy Controller Bus sniffing Scalable Coherent Interface Computing Computer hardware Computer memory
3	The NUMAchine Multiprocessor: Design and Analysis Robin Grindley A thesis submitted in conformity with the requirements Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-11-29 17:16:53 Central processing unit Parallel computing Computer memory Concurrent computing CPU cache Scalable Coherent Interface Non-Uniform Memory Access Cache coherence Microarchitecture Computing Computer hardware Computer architecture
4	The NUMAchine Multiprocessor R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vra Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 2000-09-02 04:07:38 CPU cache Non-Uniform Memory Access Cache coherence Speedup Cache-only memory architecture SMP - Symmetric Multiprocessor System Cache Memory hierarchy Scalable Coherent Interface Computing Parallel computing Computer memory
5	NUMAchine Principles of Operation for System Programmers ** THIS IS A PRELIMINARY DOCUMENT. It is continually evolving and is subject to change at any time. Steve Caranci Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:53** Computer memory CPU cache Conventional PCI Cache Dynamic random-access memory Interrupt Scalable Coherent Interface Direct memory access Computer hardware Computing Computer architecture
6	URCS Tech. Rep. 711, Aug[removed]The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory Computing1 Robert Stets, Sandhya Dwarkadas, Leonidas Kontothanassis2, Umit Rencuzog Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-31 23:40:55 Data Project management Scalability System administration Transaction processing Communications protocol ANT Distributed memory Scalable Coherent Interface Computing Concurrent computing Parallel computing
7	Microsoft Word - _Camera Ready v 1.2_ SCI_Networking_for_Shared-Memory_Computing_in_UPC_Blueprints_of_the_GASNet_SCI_Conduit.do Add to Reading List Source URL: gasnet.lbl.gov Language: English - Date: 2004-11-10 20:12:15 Computer buses Scalable Coherent Interface Myrinet InfiniBand Electrical conduit Dolphin Interconnect Solutions Low latency Transmission Control Protocol QsNet Computing Computer networks Supercomputers
8	Appeared in the Proceedings of the 20th Intl. Symp. on Computer Architecture, May[removed]The Performance of Cache-Coherent Ring-based Multiprocessors Luiz André Barroso and Michel Dubois [removed]; dubois@par Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:37:39 Parallel computing CPU cache Cache Central processing unit Scalable Coherent Interface Bus sniffing Computing Cache coherency Computer memory
9	Appeared in the IEEE Transactions on Computers, July[removed]Performance Evaluation of the Slotted Ring Multiprocessor Luiz André Barroso and Michel Dubois Department of Electrical Engineering-Systems Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:37:47 Parallel computing Scalable Coherent Interface Supercomputers Computer memory Cache coherence CPU cache Cache Linked list Bus sniffing Computing Cache coherency Concurrent computing
10	Published in ICPP’91 CACHE COHERENCE ON A SLOTTED RING Luiz A. Barroso and Michel Dubois EE-Systems Department University of Southern California Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:37:34 Bus sniffing CPU cache Cache coherence Cache Scalable Coherent Interface MESI protocol Parallel computing Firefly protocol MSI protocol Cache coherency Computing Computer hardware

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